The present invention relates to a joint system for frame rate conversion and video compression, and more particularly, to a system that shares processes of a motion estimation module and a motion compensation module between frame rate conversion and video compression operations.
Please refer to FIG. 1, which is a diagram of a conventional ME/MC frame rate conversion circuit 100 that converts a film, movie or animated source having a sample rate of 24-30 Hz into a display video stream having a sample rate of 50-60 Hz or 100-120 Hz, the frame rate conversion circuit 100 includes a motion estimation circuit 110, a motion compensation circuit 120, and a storage unit such as a DRAM 130. The DRAM 130 temporarily stores input frames, and the motion estimation circuit 110 retrieves two frames (a current frame and a previous frame) from the DRAM 130 and compares them to generate a motion vector indicating the motion of a pixel corresponding to the location movement of the pixel from a previous frame to a current frame. The motion compensation circuit 120 also retrieves the two frames from the DRAM 130, which are processed together with the motion vector received from the motion estimation circuit 110 for generating a frame to be interpolated between the current frame and the previous frame.
After carrying out the above operations, which are collectively called frame rate conversion with motion judder cancellation (MJC), the output video has a higher frame rate than the input video with reduced judder artifact. The frame rate conversion circuit 100 can therefore correctly interpolate the intermediate frames even when the objects and background in the frames are moving.
Motion estimation and motion compensation are also utilized in video coding, as shown in FIG. 2. The video encoder 200 is utilized to compress the input video stream by removing the redundancy of the input frames; in other words, the output compressed stream of the video encoder 200 that is transmitted to the receiving end only includes the difference between each two adjacent frames. The receiving end then reconstructs the original frame stream by compensating for the difference.
The video encoder 200 therefore includes a DRAM 230 for temporarily storing input frames, and a motion estimation circuit 210 for retrieving two frames (i.e. an I-frame and a P-frame) from the DRAM 230 and comparing the two frames to generate a residue and a motion vector indicating the difference between the two frames. The residue is then encoded by a block encoding circuit 240, and sent to the bit stream generator 260 to generate a compressed bit-stream. A block decoding circuit 250 and a motion compensation circuit 220 simulate the operations that the receiving end takes to reconstruct the original frame stream: the block decoding circuit 250 decodes the encoded residue, and the motion compensation circuit 220 generates a reconstructed frame according to the residue generated by the block decoding circuit 250 and the motion vectors generated by the motion estimation circuit 210. The reconstructed frame, which is utilized as the P-frame in the next encoding cycle, is stored into the DRAM 230 before being retrieved by the motion estimation circuit 210.
However, the data compression and the frame rate conversion operations are always performed independently, which considerably wastes resources and requires a large chip area for the duplicate motion estimation circuits and motion compensation circuits.